The present invention relates to next generation Double Data Rate (DDR) Synchronous Dynamic Random-Access Memories (SDRAMs); specifically DDR3 and DDR4 SDRAMs. The new generation DDR3 and DDR4 technologies operate at lower power, run at higher speeds, offer at least two-times the bandwidth, and are packed with denser circuitry than the preceding technology DDR2. The high speed and high efficiency of the DDR3 and DDR4 technology places high demand on any memory controller, in a System on a Chip (SoC). DDR3 and DDR4 interfaces require board system speeds in excess of 400 MHz that requires a new fly-by-topology be adopted to provide better signal integrity at higher speeds.
Older DDR2 technologies used a T-branch Topology. T-branch Topology required a high number of data lines going from the memory controller directly to each DRAM; this caused the clock's signal arriving time to all DRAMs on a DIMM to be roughly the same.
The new DDR3 and DDR4 fly-by topology allows the fly-by signals of command, control, and clock signals to be connected in series with each DRAM Device. This connection in series causes a delay for signals sent to each DRAM on a DIMM that is unique and different. This will now be described with reference to FIGS. 1-2.
FIG. 1 illustrates an example conventional SDRAM circuit 100.
As illustrated in the figure, conventional SDRAM circuit 100 includes a DIMM 102 and a controller 104. DIMM 102 includes a Dynamic Random-Access Memory (DRAM) 106, a DRAM 108, a DRAM 110, a DRAM 112, a DRAM 114, a DRAM 116, a DRAM 118 and a DRAM 120.
Controller 104 receives instructions from a processor (not shown) via signal line 122. Accordingly, the processor may store and retrieve data within SDRAM circuit 100. However, before storage and retrieval may be performed, DIMM 102 must be calibrated, which is the basis of the discussion herein. As such, there will be no further discussion with respect to storage and retrieval of data by the processor via signal line 122.
Controller 104 provides fly-by instructions via clock (CK) line 124 to DIMM 102. Controller 104 reads and writes data from each of DRAMs 106, 108, 110, 112, 114, 116, 118 and 120 via DQ lines (indicated by dashed arrows) 126, 128, 130, 132, 134, 136, 138 and 140, respectively. Controller provides data strobe signals to each of DRAMs 106, 108, 110, 112, 114, 116, 118 and 120 via DQS lines (indicated by solid arrows) 142, 144, 146, 148, 150, 152, 154 and 156, respectively.
It should be noted that each of a CK line and a DQS line discussed herein is actually a differential pair, which is a pair of tightly coupled carriers, one of these carrying the signal, the other carrying an equal but opposite image of the signal. Accordingly, a CK line is actually a CK line carrying the signal and a CK#line carrying an equal but opposite image of the signal. Similarly, a DQS line is actually a DQS line and a DQS#line.
Controller 104 provides fly-by instructions via clock (CK) line 124 to each of DRAMs 106, 108, 110, 112, 114, 116, 118 and 120 DRAM 108 via line 124. The path length of line 124 increases as it travels from DRAM 106 through DRAM 120. This increased path length is indicated as sections 174, 176, 178, 180, 182, 184, 186 and a terminal end 188. In particular. DRAM 108 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 106 by an amount indicated by section 174. DRAM 110 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 108 by an amount indicated by section 176. DRAM 112 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 110 by an amount indicated by section 178. DRAM 114 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 112 by an amount indicated by section 180. DRAM 116 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 114 by an amount indicated by section 182. DRAM 118 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 116 by an amount indicated by section 184. DRAM 120 is arranged to receive fly-by instructions from controller 104 via line 124, but with a path length that is longer than the path length as provided to DRAM 118 by an amount indicated by section 186. The CK line terminates at termination 188.
For each DRAM, controller 104 is able to access data stored therein via a DQ line, e.g., controller 104 may access data in DRAM 106 via DQ line 126. In order to write data into a DRAM, controller 104 sends data via a DQ line, and along with data, controller 104 sends a strobe pulse via the DQS line so that it can be captured by the DRAM. But there is one requirement from the DRAM side that CK line 124 must be properly aligned with the DQS pulse as provided in DQS line 142.
Properly aligning a CK pulse with a DQS pulse for DRAM 106 is a rudimentary procedure. However, properly aligning a CK pulse with a DQS pulse for the remaining DRAMs, respectively, may be a little more complex. In particular, in CK line 124, each of the extra path lengths indicated by sections 174, 176, 178, 180, 182, 184, 186 and 188 may have different parameters, e.g., lengths, which would provide somewhat different delays in the clock pulses as they travel from controller 104 through each DRAM to termination 188.
To compensate for the delay difference, write-leveling techniques are used. Controller 104 ensures the calibration is done automatically. During write-leveling, controller 104 compensates for the difference between the CK signal and the DQS signal to each DRAM, respectively, on DIMM 102. This difference the CK signal and the DQS signal to a DRAM, is the flight-time skew for that DRAM. As mentioned above, this flight-time skew is different for each DRAM, and is therefore uniquely adjusted for each.
Controller 104 adjusts for the flight-time skew by incrementally delaying the DQS signal one step at a time and until a transition from 0 to 1 is detected on the CK signal on destination DRAM. This realigns DQS and CK signals so that the data on DQ line is captured reliably.
Write-leveling to compensate for flight-time skew will now be further discussed with reference to FIG. 2.
FIG. 2 illustrates example clock signals and DQS signals provided to DRAM 114 of FIG. 1.
FIG. 2 includes a source CK signal 202, a source DQS signal 204, a destination CK signal 206, a destination DQS signal 208 and an aligned DQS signal 210.
Source CK signal 202 corresponds to the CK signal leaving controller 104 via CK line 124 after having traveled through extended paths indicated by sections 174, 176, 178 and 180. Source DQS signal 204 corresponds to the DQS signal leaving controller 104 via DQS line 150. Destination CK signal 206 corresponds to the CK signal arriving at DRAM 114 via CK line 124 after having traveled through extended paths indicated by sections 174, 176, 178 and 180. Destination DQS signal 208 corresponds to the DQS signal arriving at DRAM 114 via DQS line 150. It should be noted that the destination CK signal and the DQS signal may correspond to those arriving at any one of the DRAMs. Clearly each DRAM will have a different flight-time skew. In this example, aligned DQS signal 210 corresponds to a subsequently transmitted modified DQS signal arriving at DRAM 114 via DQS line 150.
Source CK signal 202 includes a plurality of pulses, a representative of which is indicated as pulse 212. Pulse 212 includes a rising edge 214 and a falling edge 216.
Source DQS signal 204 includes a plurality of pulses, a representative of which is indicated as pulse 218. Pulse 218 includes a rising edge 220 and a falling edge 222.
Destination CK signal 206 includes a plurality of pulses, a representative of which is indicated as pulse 224. Pulse 224 includes a rising edge 226 and a falling edge 228.
Destination DQS signal 208 includes a plurality of pulses, a representative of which is indicated as pulse 230. Pulse 230 includes a rising edge 232 and a falling edge 234.
Aligned DQS signal 210 includes a plurality of pulses, a representative of which is indicated as pulse 242. Pulse 242 includes a rising edge 244 and a falling edge 246.
In this example, the delay of the CK signal from controller 104 to DRAM 114, is illustrated by arrow 236, whereas the delay of the DQS signal from controller 104 to DRAM 114 is illustrated by arrow 238. The DQS delay is less than the CK delay. In other words, the DQS signal arrives at DRAM 114 ahead of the CK signal. The difference between the DQS delay and the CK delay is the flight-time skew and, in this case, is less than one clock cycle.
Now that the flight-time skew is known, controller 104 may adjust subsequent DQS signals such that they are aligned with the CK signals, i.e., the DQS delay is the same as the CK delay. This is shown in aligned DQS signal 210. Here, rising edge 232 of pulse 230 corresponds to rising edge 244 of pulse 242 of a subsequent DQS signal. Rising edge 244 of pulse 242 matches rising edge 226 of pulse 206 of destination CK signal 206.
In conventional write-leveling systems, the flight-time skew for each DRAM is determined, respectively. Then subsequent DQS signals, for each DRAM, are modified to account for the flight-time skews, respectively. This is the conventional method for correcting flight-time skew by write leveling, when the difference between the DQS delay and the CK delay is less than one clock cycle.
The conventional methods of write-leveling fail to address situations where the DQS signal arrives after the CK signal. Further, conventional methods of write-leveling fail to address situations where the difference between the DQS delay and the CK delay is more than one clock cycle.
What is needed is a write-leveling system and method that addresses situations where the DQS signal arrives after the CK signal. Further, what is needed is a write-leveling system and method that addresses situations where the difference between the DQS delay and the CK delay is more than one clock cycle.